SPI Clock & Throughput Calculator
Generated infographic and interface snapshot for SPI Clock & Throughput Calculator
Divider in, clock out — plus the real transfer time of every frame you send.
Free SPI Clock & Throughput Calculator Online — Big Das
SPI has no protocol overhead: every SCK tick moves exactly one bit. That makes it beautifully predictable — yet engineers still guess whether reading a 256-byte flash page will take 50 µs or 500 µs. Our free SPI Clock & Throughput Calculator turns your peripheral clock and divider into the realised SCK frequency, the raw throughput in Mbps and bytes per second, and the transfer time for any frame size.
What Determines SPI Clock Speed?
The SPI master derives SCK from a peripheral clock — system clock, APB clock, or CPU clock — through a hardware divider:
SCK = fCLK / divider
Most microcontrollers (STM32, AVR, MSP430) offer only powers of two: ÷2, ÷4, ÷8 … up to ÷256. Others accept arbitrary integer values. Because the choices are discrete, the exact frequency your slave allows is rarely available — you round down to the next legal divider, which is why checking every option at once matters.
Throughput follows directly: SPI is full duplex on Mosi and Miso, so each direction carries one bit per SCK edge:
- Bits per second: same as SCK in Hz
- Bytes per second: SCK / 8
- Frame time: (bytes × 8) / SCK
How to Use the Tool
- Enter the peripheral clock (with Hz/kHz/MHz units) — on STM32 SPI blocks this is the APB bus clock, which may differ from the CPU clock.
- Choose the divider scheme — powers of two for STM32/AVR-style hardware, or a custom integer divider for peripherals that support it.
- Enter a frame size in bytes — a flash page, a display framebuffer chunk, a register burst.
- Read the table of every divider with its SCK, throughput in Mbps, and bytes/sec, plus the transfer panel showing how long your frame takes at the fastest SCK.
Worked Example: Reading a Flash Page
An STM32F1 runs its SPI peripheral on APB2 at 72 MHz. The slave W25Q flash tops out at 104 MHz — no constraint here. Divider options:
- ÷2 → 36 MHz = 36 Mbps = 4.5 MB/s
- ÷4 → 18 MHz = 18 Mbps = 2.25 MB/s
- ÷8 → 9 MHz
- ÷16 → 4.5 MHz … down to ÷256 → 281.25 kHz
At ÷2, a 256-byte flash page is 2048 bits and transfers in 2048 / 36 MHz ≈ 56.9 µs. The same page on an 8 MHz AVR Arduino at ÷2 (4 MHz SCK) takes 512 µs — nearly ten times longer. Those are exactly the numbers the tool's transfer panel reports.
Raw Clock vs. Real Throughput
The figures here are raw SCK rates. Real transfers cost extra cycles:
- Chip-select setup and hold delays around the transaction.
- Software overhead — writing each byte to the data register or queuing DMA.
- Command phases — SPI flash reads prepend a 32-bit (or longer) command before data flows.
Expect sustained throughput 10–30% below the raw rate in polling drivers; DMA approaches the limit. The tool gives you the theoretical ceiling so you can judge how much your software layer is costing.
Common Use Cases
Display framebuffers (a 320×240 RGB565 frame is 150 KB — the byte rate tells you the achievable fps before you write code), SD cards and SPI flash transfers, slow slaves like EEPROMs on fast buses (the table shows the fastest legal divider at a glance), and ISR-vs-DMA budgeting: if a 1 kB burst takes 1 ms at 8 Mbps, an interrupt-per-byte driver will not keep up.
Frequently Asked Questions
Why can I not get exactly 10 MHz SCK?
Reachability is limited to discrete divisors. On power-of-two hardware a 72 MHz clock yields 36, 18, 9, 4.5 MHz… — so 10 MHz isn't available; you get 9 MHz (÷8). The table lists every reachable frequency; pick the fastest one at or below your slave's maximum.
Is SPI throughput the SCK frequency?
Yes — per data line. SPI transfers one bit per SCK edge, so 20 MHz SCK is 20 Mbps = 2.5 MB/s in each direction simultaneously. Dual- and quad-SPI modes (common on flash chips) multiply the byte rate by 2 or 4; multiply the tool's result accordingly.
Which clock do I enter — CPU or APB?
The clock feeding the SPI peripheral itself. On many STM32 parts, SPI1 sits on APB2 at full main-clock speed while SPI2/3 sit on the slower APB1. Check the clock tree in your datasheet — using the wrong input clock is the most common source of wrong SCK.
What if my peripheral supports any integer divider?
Switch the divider scheme to custom integer, enter your divider, and the tool computes SCK, throughput and frame time for exactly that configuration.